cy7c109bn, cy7c1009bn 128k x 8 static ram cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document #: 001-06430 rev. *b revised april 5, 2010 features high speed ? t aa = 15 ns low active power ? 440 mw (maximum 15 ns) low cmos standby power ? 55 mw (maximum) 4 mw 2.0v data retention automatic power down when deselected ttl-compatible inputs and outputs easy memory expansion with ce 1 , ce 2 , and oe options functional description the cy7c109bn/cy7c1009bn [1] is a high performance cmos static ram organized as 131,072 words by 8 bits. easy memory expansion is provided by an active low chip enable (ce 1 ), an active high ch ip enable (ce 2 ), an active low output enable (oe ), and three-state drivers. writing to the device is accom- plished by taking chip enable one (ce 1 ) and write enable (we ) inputs low and chip enable two (ce 2 ) input high. data on the eight i/o pins (i/o 0 through i/o 7 ) is then written into the location specified on the address pins (a 0 through a 16 ). reading from the device is accomplished by taking chip enable one (ce 1 ) and output enable (oe ) low while forcing write enable (we ) and chip enable two (ce 2 ) high. under these conditions, the contents of the memory location specified by the address pins appear on the i/o pins. the eight input/output pins (i/o 0 through i/o 7 ) are placed in a high impedance state when the device is deselected (ce 1 high or ce 2 low), the outputs are disabled (oe high), or during a write operation (ce 1 low, ce 2 high, and we low). the cy7c109bn is available in standard 400-mil-wide soj and 32-pin tsop type i packages. the cy7c1009bn is available in a 300-mil-wide soj package. the cy7c1009bn and cy7c109bn are functionally equivalent in all other respects. note 1. for guidelines on sram system design, refer to the ?system design guidelines? cypress applicati on note, available on the inte rnet at www.cypress.com . 14 15 a 1 a 2 a 3 a 4 a 5 a 6 a 7 a 8 column decoder r ow decoder sen se amps input buffer power down we oe i/o 0 ce 2 i/o 1 i/o 2 i/o 3 512x 256 x 8 array i/o 7 i/o 6 i/o 5 i/o 4 a 0 a 11 a 13 a 12 a a 10 ce 1 a a 16 a 9 logic block diagram [+] feedback
cy7c109bn, cy7c1009bn document #: 001-06430 rev. *b page 2 of 9 pin configurations figure 1. 32-pin soj (topview) 1 2 3 4 5 6 7 8 9 10 11 14 19 20 24 23 22 21 25 28 27 26 13 29 32 31 30 16 15 17 18 gnd a 16 a 14 a 12 a 7 a 6 a 5 a 4 a 3 we v cc a 15 a 13 a 8 a 9 i/o 7 i/o 6 i/o 5 i/o 4 a 2 nc i/o 0 i/o 1 i/o 2 ce 1 oe a 10 i/o 3 a 1 a 0 a 11 ce 2 selection guide description 7c109b-15 7c1009b-15 7c109b-20 7c1009b-20 unit maximum access time 15 20 ns maximum operating current 80 75 ma maximum cmos standby current 10 10 ma l 2 2 ma [+] feedback
cy7c109bn, cy7c1009bn document #: 001-06430 rev. *b page 3 of 9 maximum ratings exceeding maximum ratings may shorten the useful life of the device. user guidelines are not tested. storage temperature ................................. ?65 ? c to +150 ? c ambient temperature with power applied ............................................ ?55 ? c to +125 ? c supply voltage on v cc to relative gnd [2] .....?0.5v to +7.0v dc voltage applied to outputs in high z state [2] .................................... ?0.5v to v cc + 0.5v dc input voltage [2] ................................ ?0.5v to v cc + 0.5v current into outputs (low)..... .................................... 20 ma static discharge voltage....... ........... ............ .............. >2001v (per mil-std-883, method 3015) latch up current ..................................................... >200 ma operating range range ambient temperature v cc commercial 0 ? c to +70 ? c 5v ? 10% industrial ? 40 ? c to +85 ? c 5v ? 10% notes 2. minimum voltage is ?2.0v for pulse durations of less than 20 ns. 3. not more than one output should be shorted at one time. du ration of the short circuit s hould not exceed 30 seconds. 4. tested initially and after any design or proce ss changes that may affect these parameters. electrical characteristics over the operating range parameter description test conditions 7c109bn-15 7c1009bn-15 7c109bn-20 7c1009bn-20 unit min max min max v oh output high voltage v cc = min, i oh = ?4.0 ma 2.4 2.4 v v ol output low voltage v cc = min, i ol = 8.0 ma 0.4 0.4 v v ih input high voltage 2.2 v cc + 0.3 2.2 v cc + 0.3 v v il input low voltage [2] ?0.3 0.8 ?0.3 0.8 v i ix input leakage current gnd < v i < v cc ?1 +1 ?1 +1 ? a i oz output leakage current gnd < v i < v cc , output disabled ?5 +5 ?5 +5 ? a i os output short circuit current [3] v cc = max, v out = gnd ?300 ?300 ma i cc v cc operating supply current v cc = max, i out = 0 ma, f = f max = 1/t rc 80 75 ma i sb1 automatic ce power down current ?ttl inputs max v cc , ce 1 > v ih or ce 2 < v il , v in > v ih or v in < v il , f = f max 40 30 ma i sb2 automatic ce power down current ?cmos inputs max v cc , ce 1 > v cc ? 0.3v, or ce 2 < 0.3v, v in > v cc ? 0.3v, or v in < 0.3v, f = 0 10 10 ma l2 2ma capacitance the following are the input and outpiut capacitance test conditions. [4] parameter description test conditions max unit c in input capacitance t a = 25 ? c, f = 1 mhz, v cc = 5.0v 9pf c out output capacitance 8 pf [+] feedback
cy7c109bn, cy7c1009bn document #: 001-06430 rev. *b page 4 of 9 figure 2. ac test loads and waveforms 90% 10% 3.0v gnd 90% 10% all input pulses 5v output 30 pf including jig and scope 5v output 5 pf including jig and scope (a) (b) ?? 3 ns ? 3 ns output r1 480 ? r1 480 ? r2 255 ? r2 255 ? 167 ? equivalent to: venin equivalent 1.73v th switching characteristics [5] over the operating range parameter description 7c109bn-15 7c1009bn-15 7c109bn-20 7c1009bn-20 unit min max min max read cycle t rc read cycle time 15 20 ns t aa address to data valid 15 20 ns t oha data hold from address change 3 3 ns t ace ce 1 low to data valid, ce 2 high to data valid 15 20 ns t doe oe low to data valid 7 8 ns t lzoe oe low to low z 0 0 ns t hzoe oe high to high z [6, 7] 7 8 ns t lzce ce 1 low to low z, ce 2 high to low z [7] 3 3 ns t hzce ce 1 high to high z, ce 2 low to high z [6, 7] 7 8 ns t pu ce 1 low to power up, ce 2 high to power up 0 0 ns t pd ce 1 high to power down, ce 2 low to power down 15 20 ns write cycle [8] t wc write cycle time [9] 15 20 ns t sce ce 1 low to write end, ce 2 high to write end 12 15 ns t aw address setup to write end 12 15 ns t ha address hold from write end 0 0 ns t sa address setup to write start 0 0 ns t pwe we pulse width 12 12 ns t sd data setup to write end 8 10 ns t hd data hold from write end 0 0 ns t lzwe we high to low z [7] 3 3 ns t hzwe we low to high z [6, 7] 7 8 ns notes 5. test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5v, input pulse levels of 0 to 3. 0v, and output loading of the specified i ol /i oh and 30-pf load capacitance. 6. t hzoe , t hzce , and t hzwe are specified with a load capacitance of 5 pf as in part (b) of ac test loads. transition is measured ? 500 mv from steady-state voltage. 7. at any given temperature and voltage condition, t hzce is less than t lzce , t hzoe is less than t lzoe , and t hzwe is less than t lzwe for any given device. 8. the internal write time of the memory is defined by the overlap of ce 1 low, ce 2 high, and we low. ce 1 and we must be low and ce 2 high to initiate a write, and the transition of any of these signals can terminate the write. the input data setup and hold timing should be refer enced to the leading edge of the signal that terminates the write. 9. the minimum write cycle time for write cycle no. 3 (we controlled, oe low) is the sum of t hzwe and t sd . [+] feedback
cy7c109bn, cy7c1009bn document #: 001-06430 rev. *b page 5 of 9 data retention characteristics over the operating range (low power version only) parameter description conditions min max unit v dr v cc for data retention no input may exceed v cc + 0.5v v cc = v dr = 2.0v, ce 1 > v cc ? 0.3v or ce 2 < 0.3v, v in > v cc ? 0.3v or v in < 0.3v 2.0 v i ccdr data retention current 150 ? a t cdr chip deselect to data retention time 0 ns t r operation recovery time 200 ? s figure 3. data retention waveform switching waveforms figure 4. read cycle no. 1 [10, 11] figure 5. read cycle no. 2 (oe controlled) [11, 12] notes 10. device is continuously selected. oe , ce 1 = v il , ce 2 = v ih . 11. we is high for read cycle. 12. address valid prior to or coincident with ce 1 transition low and ce 2 transition high. 4.5v 4.5v ce v cc t cdr v dr > 2v data retention mode t r previous data valid data valid t rc t aa t oha address data out 50% 50% data valid t rc t ace t doe t lzoe t lzce t pu high impedance t hzoe t hzce t pd high oe ce 1 i cc i sb impedance address ce 2 data out v cc supply current [+] feedback
cy7c109bn, cy7c1009bn document #: 001-06430 rev. *b page 6 of 9 figure 6. write cycle no. 1 (ce 1 or ce 2 controlled) [13, 14] figure 7. write cycle no. 2 (we controlled, oe high during write) [13, 14] notes 13. data i/o is high impedance if oe = v ih . 14. if ce 1 goes high or ce 2 goes low simultaneously with we going high, the output remains in a high-impedance state. 15. during this period the i/os are in the output state and input signals should not be applied. switching waveforms (continued) t wc data valid t aw t sa t pwe t ha t hd t sd t sce t sce ce 1 address ce 2 we data i/o t hd t sd t pwe t sa t ha t aw t sce t sce t wc t hzoe data in valid ce 1 address ce 2 we data i/o oe note 15 [+] feedback
cy7c109bn, cy7c1009bn document #: 001-06430 rev. *b page 7 of 9 figure 8. write cycle no. 3 (we controlled, oe low) [14] switching waveforms (continued) data valid t hd t sd t lzwe t pwe t sa t ha t aw t sce t sce t wc t hzwe ce 1 address ce 2 we data i/o note 15 truth table ce 1 ce 2 oe we i/o 0 ?i/o 7 mode power h x x x high z power down standby (i sb ) x l x x high z power down standby (i sb ) l h l h data out read active (i cc ) l h x l data in write active (i cc ) l h h h high z selected, outputs disabled active (i cc ) ordering information speed (ns) ordering code package diagram package type operating range 15 CY7C1009BN-15VI 51-85041 32-pin (300-mil) molded soj industrial 20 cy7c109bn-20vi 51-85033 32-pin (400-mil) molded soj industrial contact your local sales representativ e regarding availability of these parts [+] feedback
cy7c109bn, cy7c1009bn document #: 001-06430 rev. *b page 8 of 9 package diagrams figure 9. 32-pin (300-mil) molded figure 10. 32-pin (400-mil) molded soj 51-85041 *b 51-85033 *c [+] feedback
document #: 001-06430 rev. *b revised april 5, 2010 page 9 of 9 all products and company names mentioned in this document may be the trademarks of their respective holders. cy7c109bn, cy7c1009bn ? cypress semiconductor corporation, 2006-2010. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement wi th cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. document history page sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representative s, and distributors. to find t he office closest to you, visit us at cypress.com/sales. products psoc psoc.cypress.com clocks & buffers clocks.cypress.com wireless wireless.cypress.com memories memory.cypress.com image sensors image.cypress.com document title: cy7c109bn / cy7c1009bn 128k x 8 static ram document number: 001-06430 rev. ecn no. orig. of change submission date description of change ** 423847 nxr see ecn new data sheet *a 2755340 nxr 08/24/2009 removed -12 from pro duct offering as 12ns parts are not active corrected package diagram updated ordering information *b 2904565 aju 04/05/10 removed inactive part numbe r from the ordering information table.updated package diagrams. [+] feedback
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